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description designed for pulse width modulated (pwm) current control of dc motors, the a3959 is capable of output currents to 3 a and operating voltages to 50 v. internal fixed off-time pwm current- control timing circuitry can be adjusted via control inputs to operate in slow, fast, and mixed current-decay modes. phase and enable input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied pwm-control signals. internal synchronous rectification control circuitry is provided to reduce power dissipation during pwm operation. internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of supply and charge pump, and crossover-current protection. special power-up sequencing is not required. the a3959 provides a choice of three power packages, a 24-pin dip with batwing tabs (package suffix ?b?), a 24-lead soic with four internally-fused pins (package suffix ?lb?), and a thin (<1.2 mm) 28-pin tssop with an exposed thermal pad (suffix ?lp?). in all cases, the power pins and tabs are at ground potential and need no electrical isolation. each package is lead (pb) free, with 100% matte tin leadframes. 29319.37l features and benefits ? 3 a, 50 v output rating ? low r ds(on) outputs (270 m ? , typical) ? mixed, fast, and slow current-decay modes ? synchronous rectification for low power dissipation ? internal uvlo and thermal-shutdown circuitry ? crossover-current protection ? internal oscillator for digital pwm timing dmos full-bridge pwm motor driver packages: functional block diagram not to scale a3959 package lp, 28-pin tssop with exposed thermal pad package b, 24-pin dip with exposed tabs package lb, 24-pin soic with internally fused pins charge pump bandgap v dd c reg tsd under- voltage & fault detect charge pump bandgap regulator v dd v bb + logic supply v reg cp1 cp cp2 load supply gate drive dwg. fp-048-2a control logic sense r s sleep ext mode phase enable blank pfd1 pfd2 reference buffer & w 10 current sense zero current detect out a out b ref pwm timer v ref c s osc rosc to v dd to v dd
dmos full-bridge pwm motor driver a3959 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number package packing A3959SB-T 24-pin dip with exposed tabs 15 per tube a3959slbtr-t 24-pin soic with internally fused pins 1000 per reel a3959slptr-t 28-pin tssop with exposed thermal pad 4000 per reel absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 50 v logic supply voltage v dd 7.0 v input voltage v in continuous ?0.3 to v dd + 0.3 v t w < 30 ns ?1.0 to v dd + 1.0 v sense voltage v s continuous 0.5 v t w < 3 s 2.5 v reference voltage v ref v dd v output current i out output current rating may be limited by duty cycle, am- bient temperature, and heat sinking. under any set of conditions, do not exceed the speci ed current rating or a junction temperature of 150 c. repetitive 3.0 a peak, < 3 s 6.0 a package power dissipation p d see thermal characteristics ? ? operating ambient temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) fault conditions that produce excessive junction temperature will activate the device?s thermal shutdown circuitry. these conditions can be toler- ated but should be avoided. 150 oc storage temperature t stg ?55 to 150 oc
dmos full-bridge pwm motor driver a3959 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 50 75 100 125 150 5 1 0 allowable package power dissipation (w) temperature in o o o o c 4 3 2 25 suffix 'b', r q ja = 36 o c/w suffix 'lp', r q ja = 40 o c/w suffix 'lb', r q ja = 51 o c/w 2-layer board, 1 sq. in. copper ea. side suffix 'b', r q ja = 26 o c/w suffix 'lp', r q ja = 28 o c/w suffix 'lb', r q ja = 35 o c/w 4-layer board thermal characteristics characteristic symbol test conditions value units package power dissipation p d b package 3.3 w lb package 2.5 w lp package 3.1 w package thermal resistance, junction to ambient r ja b package 1-layer pcb, minimal exposed copper area 54 oc/w 2-layer pcb, 1-in. 2 2-oz copper exposed area 36 oc/w 4-layer pcb, based on jedec standard 26 oc/w lb package 1-layer pcb, minimal exposed copper area 77 oc/w 2-layer pcb, 1-in. 2 2-oz copper exposed area 51 oc/w 4-layer pcb, based on jedec standard 35 oc/w lp package 1-layer pcb, minimal exposed copper area 100 oc/w 2-layer pcb, 1-in. 2 2-oz copper exposed area 40 oc/w 4-layer pcb, based on jedec standard 28 oc/w package thermal resistance, junction to tab r jt b and lb packages 6 oc/w package thermal resistance, junction to pad r jp lp package 2 oc/w *additional thermal information available on allegro website.
dmos full-bridge pwm motor driver a3959 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com continued next page ? characteristics symbol test conditions min. typ. max. units output drivers load supply voltage range v bb operating 9.5 ? 50 v during sleep mode 0 ? 50 v output leakage current i dss v out = v bb ? <1.0 20 a v out = 0 v ? <-1.0 -20 a output on resistance r ds(on) source driver, i out = -3 a ? 270 300 m sink driver, i out = 3 a ? 270 300 m crossover delay 300 600 1000 ns body diode forward voltage v f source diode, i f = -3 a ? ? 1.6 v sink diode, i f = 3 a ? ? 1.6 v load supply current i bb f pwm < 50 khz ? 4.0 7.0 ma charge pump on, outputs disabled ? 2.0 5.0 ma sleep mode ? ? 20 a control logic logic supply voltage range v dd operating 4.5 5.0 5.5 v logic input voltage v in(1) 2.0 ? ? v v in(0) ? ? 0.8 v logic input current (all inputs except enable) i in(1) v in = 2.0 v ? <1.0 20 a i in(0) v in = 0.8 v ? <-2.0 -20 a logic supply current i dd f pwm < 50 khz ? 6.0 10 ma sleep mode ? ? 2.0 ma enable input current i in(1) v in = 2.0 v ? 40 100 a i in(0) v in = 0.8 v ? 16 40 a internal osc frequency f osc rosc shorted to ground 3.25 4.25 5.25 mhz rosc = 51 k 3.65 4.25 4.85 mhz reference input volt. range v ref operating 0.0 ? v dd v reference input current i ref v ref = v dd ? ? 1.0 a comparator input offset voltage v io v ref = 0 v ? 5.0 ? mv electrical characteristics at t a = +25c, v bb = 50 v, v dd = 5.0 v, v sense = 0.5 v, f pwm < 50 khz (unless noted otherwise)
dmos full-bridge pwm motor driver a3959 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) at t a = +25c, v bb = 50 v, v dd = 5.0 v, v sense = 0.5 v, f pwm < 50 khz (unless noted otherwise) characteristics symbol test conditions min. typ. max. units reference divider ratio ? ? 10 ? ? gm error (note 3) e gm v ref = v dd ? ? 4.0 % v ref = 0.5 v ? ? 14 % propagation delay times t pd 0.5 e in to 0.9 e out : pwm change to source on 600 750 1200 ns pwm change to source off 50 150 350 ns pwm change to sink on 600 750 1200 ns pwm change to sink off 50 100 150 ns thermal shutdown temp. t j ? 165 ? c thermal shutdown hysteresis ? t j ?15 ? c uvlo enable threshold uvlo increasing v dd 3.90 4.2 4.45 v uvlo hysteresis ? uvlo 0.05 0.10 ? v notes: 1. typical data is for design information only. 2. negative current is de ned as coming out of (sourcing) the speci ed device terminal. 3. g m error = ([v ref /10] ? v sense )/(v ref /10) where v sense = i trip ?r s .
dmos full-bridge pwm motor driver a3959 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description v reg . this internally generated voltage is used to operate the sink-side dmos outputs. the v reg terminal should be decoupled with a 0.22 f capacitor to ground. v reg is internally monitored and in the case of a fault condition, the outputs of the device are disabled. charge pump. the charge pump is used to generate a gate-supply voltage greater than v bb to drive the source- side dmos gates. a 0.22 f ceramic capacitor should be connected between cp1 and cp2 for pumping purposes. a 0.22 f ceramic capacitor should be connected between cp and v bb to act as a reservoir to operate the high-side dmos devices. the cp voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. phase logic. the phase input terminal determines if the device is operating in the ?forward? or ?reverse? state. phase out a out b 0 low high 1 high low enable logic. the enable input terminal allows external pwm. enable high turns on the selected sink- source pair. enable low switches off the source driver or the source and sink driver, depending on ext mode, and the load current decays. if enable is kept high, the current will rise until it reaches the level set by the internal current-control circuit. enable outputs 0 chopped 1 on ext mode logic. when using external pwm current control, the ext mode input determines the current path during the chopped cycle. with ext mode low, fast decay mode, the opposite pair of selected outputs will be enabled during the off cycle. with ext mode high, slow decay mode, both sink drivers are on with enable low. ext mode decay 0 fast 1 slow current regulation. load current is regulated by an internal xed off-time pwm control circuit. when the outputs of the dmos h bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (r s ) and the applied analog reference voltage (v ref ): i trip = v ref /10r s at the trip point, the sense comparator resets the source- enable latch, turning off the source driver. the load inductance then causes the current to recirculate for the xed off-time period. the current path during recirculation is determined by the con guration of slow/mixed/fast current-decay mode via pfd1 and pfd2. oscillator. the pwm timer is based on an internal oscillator set by a resistor connected from the r osc terminal to v dd . typical value of 4 mhz is set with a 51 k resistor. the allowable range of the resistor is from 20 k to 100 k . f osc = 204 x 10 9 /r osc . if r osc is not pulled up to v dd , it must be shorted to ground. fixed off time. the a3959 is set for a xed off time of 96 cycles of the internal oscillator, typically 24 s with a 4 mhz oscillator.
dmos full-bridge pwm motor driver a3959 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description (continued) internal current-control mode. inputs pfd1 and pfd2 determine the current-decay method after an overcurrent event is detected at the sense input. in slow- decay mode, both sink drivers are turned on for the xed off-time period. mixed-decay mode starts out in fast-decay mode for a portion (15% or 48%) of the xed off time, and then is followed by slow decay for the remainder of the period. pfd2 pfd1 % t off decay 0 0 0 slow 0 1 15 mixed 1 0 48 mixed 1 1 100 fast pwm blank timer. when a source driver turns on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. to prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. the blank timer runs after the off-time counter to provide the blanking function. the blank timer is reset when enable is chopped or phase is changed. for external pwm control, a phase change or enable on will trigger the blanking function. the duration is determined by the blank input and the oscilator. blank t blank 0 6/f osc 1 12/f osc synchronous recti cation. when a pwm off cycle is triggered, either by an enable chop command or internal xed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. the a3959 synchronous recti cation feature will turn on the appropriate pair of dmos outputs during the current decay and effectively short out the body diodes with the low r ds(on) driver. this will reduce power dissipation signi cantly and can eliminate the need for external schottky diodes. synchronous recti cation will prevent reversal of load current by turning off all outputs when a zero-current level is detected. shutdown. in the event of a fault (excessive junction temperature, or low voltage on cp or v reg ) the outputs of the device are disabled until the fault condition is removed. at power up, and in the event of low v dd , the uvlo circuit disables the drivers. braking. the braking function is implemented by driving the device in slow-decay mode via extmode and applying an enable chop command. because it is possible to drive current in either direction through the dmos drivers, this con guration effectively shorts out the motor-generated bemf as long as the enable chop mode is asserted. it is important to note that the internal pwm current-control circuit will not limit the current when braking, because the current does not ow through the sense resistor. the maximum brake current can be approximated by v bemf /r l . care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads. sleep logic. the sleep input terminal is used to minimize power consumption when when not in use. this disables much of the internal circuitry including the regulator and charge pump. logic low will put the device into sleep mode, logic high will allow normal operation. note: if the sleep mode is not used, connect a 5 k pull- up resistor between the sleep terminal and v dd .
dmos full-bridge pwm motor driver a3959 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description (continued) current sensing. to minimize inaccuracies in sensing the i trip current level, which may be caused by ground trace ir drops, the sense resistor should have an independent ground return to the ground terminal of the device. for low-value sense resistors the ir drops in the pcb sense resistor?s traces can be signi cant and should be taken into account. the use of sockets should be avoided as they can introduce variation in r s due to their contact resistance. the maximum value of r s is given as r s = 0.5/i trip . thermal protection. circuitry turns off all drivers when the junction temperature reaches 165c typically. it is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. thermal shutdown has a hysteresis of approximately 15c. layout. a star ground system located close to the driver is recommended. the printed wiring board should use a heavy ground plane. for optimum electrical and thermal performance, the driver should be soldered directly onto the board. the ground side of r s should have an indi- vidual path to the ground terminals of the device. this path should be as short as is possible physically and should not have any other components connected to it. it is recom- mended that a 0.1 f capacitor be placed between sense and ground as close to the device as possible; the load sup- ply terminal, v bb , should be decoupled with an electrolyt- ic capacitor (> 47 f is recommended) placed as close to the device as is possible. on the 28-lead tssop package, the copper ground plane located under the exposed thermal pad is typically used as a star ground.
dmos full-bridge pwm motor driver a3959 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pwm timer v bb 24 23 22 21 28 27 26 25 20 17 16 15 nc sense sleep no connection out b nc load supply nc out a no connection ext mode ref v reg 1 2 3 4 5 8 9 12 11 14 13 10 ground ground ground cp cp 2 cp 1 phase nc nc v dd enable pfd 2 blank pfd 1 logic supply q rosc logic nc nc charge pump 10 6 7 19 18 terminal list package b (dip) pwm timer 10 v bb 24 23 22 21 20 19 18 17 16 15 14 13 ground ground sleep v reg out b load supply sense out a ext mode ref dwg. pp-069-5a 1 2 3 4 5 6 7 8 9 12 11 10 9 ground ground cp cp 2 cp 1 phase v dd logic supply enable pfd 2 blank pfd 1 ? rosc logic charge pump ground ground package lb (soic) pwm timer v bb 24 23 22 21 20 17 16 15 14 13 ground ground sleep no connection out b load supply sense out a no connection ext mode ref v reg dwg. pp-069-4 1 2 3 4 5 8 9 12 11 10 ground ground cp cp 2 cp 1 phase v dd enable pfd 2 blank pfd 1 logic supply q rosc logic nc nc charge pump 10 6 7 19 18 package lp (tssop) terminal name terminal description b (dip) lb (soic) lp (tssop) cp reservoir capacitor (typically 0.22 f) 24 1 1 cp1 & cp2 the charge pump capacitor (typically 0.22 f) 1 & 2 2 & 3 2 & 3 nc no (internal) connection ? ? 4 phase logic input for direction control 3 4 5 rosc oscillator resistor 4 5 6 ground grounds 5, 6, 7, 8* 6, 7 7, 8* logic supply vdd, the low voltage (typically 5 v) supply 9 8 9 enable logic input for enable control 10 9 10 nc no (internal) connection ? ? 11 pfd2 logic-level input for fast decay 11 10 12 blank logic-level input for blanking control 12 11 13 pfd1 logic-level input for fast decay 13 12 14 ref vref, the load current reference input voltage 14 13 15 ext mode logic input for pwm mode control 15 14 16 no connect no (internal) connection ? 15 17 outa one of two dmos bridge outputs to the motor 16 16 18 nc no (internal) connection ? ? 19, 20 sense sense resistor 17 17 21 nc no (internal) connection ? ? 22 ground grounds 18, 19* 18, 19 ? load supply vbb, the high-current, 9.5 v to 50 v, motor supply 20 20 23 outb one of two dmos bridge outputs to the motor 21 21 24 no connect no (internal) connection ? 22 25 sleep logic-level input for sleep operation 22 23 26 vreg regulator decoupling capacitor (typically 0.22 f) 23 24 27 ground ground ? ? 28* * for the b (dip) package only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5 and 8. pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. for the lp (tssop) package, the grounds at term inals 7, 8, and 28 should be connected together at the exposed pad beneath the device.
dmos full-bridge pwm motor driver a3959 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com b package 24-pin dip lb package 24-pin soicw 2 0.018 1 24 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-001 be) dimensions in millimeters 5.33 max 0.46 0.12 1.27 min 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 30.10 +0.25 ?0.64 1.52 +0.25 ?0.38 0.38 +0.10 ?0.05 7.62 2.54 1.27 0.25 b reference pad layout (reference ipc soic127p1030x265-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b 0.20 0.10 0.41 0.10 2.20 0.65 9.60 1.27 2 1 24 a 15.400.20 2.65 max 10.300.33 7.500.10 c seating plane c 0.10 24x for reference only pins 6 and 7, and 18 and 19 internally fused dimensions in millimeters (reference jedec ms-013 ad) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area gauge plane seating plane pcb layout reference view 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43
dmos full-bridge pwm motor driver a3959 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2001-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com lp package 28-pin tssop 1.20 max 0.10 max c seating plane c 0.10 28x 6.10 0.65 0.45 1.65 3.00 3.00 5.00 5.00 0.25 0.65 2 1 28 gauge plane seating plane b a 28 2 1 a terminal #1 mark area b for reference only (reference jedec mo-153 aet) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 sop65p640x120-29cm); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) 4.40 0.10 6.40 0.20 (1.00) 9.70 0.10 c c 0.60 0.15 4 4 0.15 +0.05 ?0.06 0.25 +0.05 ?0.06

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